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| Fact Sheet MPC8560 POWERQUICCTM INTEGRATED COMMUNICATIONS PROCESSOR OVERVIEW TYPICAL APPLICATIONS The PowerQUICC IIITM is a verstile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications, excelling particularly in communications and networking products. Motorola's PowerQUICC III processor family is the next generation of Motorola's leading PowerQUICC line of integrated communications processors. The PowerQUICC III provides higher performance in all areas of device operation, including greater flexibility, extended capabilities, and higher integration. PRODUCT HIGHLIGHTS * Remote access concentrators/servers * Regional office routers * Wireless infrastructure equipment * Telecommunications switching and transmission equipment * Ethernet switches * T1/E1 and T3/E3 Line Cards * OC-3 Line Card * LAN- to WAN-router * DSLAMs * Multi-service access platforms * Optical Networking * IP Networking * SONET transmission controller * Media Gateways * IP Virtual Private Networks (VPN) Motorola's leading PowerQUICC III architecture integrates two processing blocks. One block is a high-performance embedded e500 core. With 256 KB of Level 2 cache, the e500 core implements the enhanced PowerPC Book E instruction-set architecture and provides unprecedented levels of hardware and software debugging support. The second block is the Communications Processor Module (CPM). The CPM of the PowerQUICC III can support three fast serial communications controllers (FCCs), two multichannel controllers (MCCs), four serial communications controllers (SCCs), one serial peripheral interface (SPI), and one I2C interface. The PowerQUICC III also offers two integrated 10/100/1000 Ethernet controllers, a DDR SDRAM memory controller, a 64-bit PCI-X/PCI controller, and a RapidIOTM interconnect. This high level of integration helps simplify board design and offers significant bandwidth and performance for high-end controlplane and data-plane applications. I2C Controller Interrupt Controller DDR SDRAM Controller Local Bus Controller 256 KB L2 cache/ SRAM Coherency Module e500 Core 32 KB L1 I cache 32 KB L1 D cache Core Complex Bus CPM TC-Layer Time Slot Assigner Time Slot Assigner MCC MCC FCC FCC FCC SCC SCC SCC SCC SPI I2C Serial DMA ROM I-mem DPRAM RISC Engine Parallel I/O Baud Rate Generators Timers RapidIOTM Controller PCI-X/PCI Controller DMA Controller Serial Interfaces 10/100/1000 MAC 10/100/1000 MAC TECHNICAL SPECIFICATIONS * Embedded e500 Book E compatible core available from 600 MHz up to 1 GHz - 32-bit, dual-issue, superscalar, seven-stage pipeline - 1850 MIPS at 800 MHz (est. Dhrystone 2.1) - 32 KB L1 data and 32 KB L1 instruction cache with line locking support - 256 KB on-chip L2 cache with direct mapped capability - Enhanced hardware and software debug support - Memory management unit (MMU) - SIMD extension with single precision floating point * High-performance RISC CPM available at up to 333 MHz - CPM software compatibility with previous families - Greater than 1 Gbps aggregate CPM bandwidth - 32 KB of dual-port RAM - 128 KB of ROM + 32 KB of RAM for protocol microcode storage - Two UTOPIA Level II master/slave ports with multi-PHY support (one can be 16-bit) - Three MII interfaces - Eight TDM interfaces (T1/E1), two TDM ports that can be interfaced with T3/E3 PowerQUICC IIITM Core Core I-Cache/D-Cache (KB) I-Cache/D-Cache (KB) IntegratedIntegrated (KB) L2 Cache L2 Cache (KB) Fast Communications Controllers Fast Communications Controllers Serial Communications Controllers Serial Controllers Ethernet (10/100) Ethernet (10/100 only) Ethernet (10/100/1000) (10/100/1000) Ethernet Utopia Level II Utopia Level II Ports Ports Multi-Channel Multi-Channel HDLC HDLC PCI-X/PCI Interface PCI-X/PCI Interface RapidIO InterfaceRapidIO Interface MPX Interface IMA Functionality IMA Functionality TC-Layer Capabilities TC-Layer Capabilities MPC8560 e500 32/32 256 3 4 up to 3 2 2 up to 256 Yes Yes Yes Yes MPC8540 e500 32/32 256 1 2 Yes Yes - - Four SCCs supporting HDLC and SDLC, HDLC bus, UART, Transparent, BISYNC - Three FCCs supporting: - Up to 155 Mbps ATM SAR-AAL0, AAL1, AAL2, AAL3/4, AAL5 - 10/100 Mbps Ethernet (up to three) IEEE 802.3X - 45 Mbps HDLC/transparent (up to three) - Two MCCs each supporting 128 full-duplex, 64 kbps, HDLC lines for a total of 256 channels - ATM transmission convergence layer capabilities (8 channels) - Integrated inverse multiplexing for ATM (IMA) functionality * Two TSECs supporting 10/100/1000 Mbps Ethernet (IEEE 802.3, 802.3u, 802.3x, 802.3z, and 802.3ac compliant) with two GMII/TBI/RGMII interfaces * 166 MHz, 64-bit, 2.5V I/O, DDR SDRAM memory controller with full ECC support * 500 MHz, 8-bit, LVDS I/O, RapidIO controller * 133 MHz, 64-bit, 3.3V I/O, PCI-X 1.0a/PCI 2.2 bus controller * 166 MHz, 32-bit, 3.3V I/O, local bus with memory controller * Integrated four-channel DMA controller * Interrupt controller * IEEE 1149.1 JTAG test access port * 1.2V core power supply with 3.3V and 2.5V I/O * 783-pin FC-BGA package MPC 8560 C PX xy CPU/Bus Speed A Die Mask Revision 8560 Family Device Number Package (8560, 8540) Temp. Range Product Code None 0C to +105C KXPC Sample Pack (2-10) C -40C to +105C XPC Engineering Production MPC Full Production MOTOROLA and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. All other product or service names are the property of their respective owners. (c) Motorola, Inc. 2002. MPC8560FACT/D REV 2 |
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